One of the metrics employed in designing a clocking architecture is skew (i.e., phase mismatch), both on the local level and on the global level. A clocking architecture may use a spine based topology, which may suffer from delay deltas due to clock paths with nominally different delays. For example, when clock root-to-load paths go through a varying number of clock spines, different delays among different clock regions in the clocking architecture may result. A clocking architecture may also suffer from process, voltage, and temperature (PVT) mismatch, even along otherwise identical paths. As a result, hold time violations are common across clock region boundaries in a clocking architecture and between dies, due to local skew problems. In addition, the performance of a clocking architecture may degrade, especially in higher speed designs, due to large global skews.
Also, a mesh deskew clock architecture has been proposed that relies on H-tree distribution to deliver a clock signal to clock regions in the clock architecture nearly simultaneously, and then use metal grid structures to deliver clock signals within a clock region. The problem with this technique is that H-trees are expensive to implement, both in terms of upper metal track usage and rebuffer transistor costs. In addition, an H-tree may increase injection delay, which correlates to increased jitter. In some cases, a particular circuit design may have multiple clock trees. Thus, any clocking costs attributable to H-tree are multiplied by the number of clock trees being implemented, which may be significant.